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Computers without clocks (2002) [pdf]

89 点作者 dluc大约 6 年前

4 条评论

nbingham大约 6 年前
Heyo, I&#x27;m a PhD student in the field. I figured I can talk about its current status.<p>First, here are various search terms: clockless, self-timed, delay-insensitive, latency-insensitive, quasi delay-insensitive (QDI), speed independent, asynchronous, bundled-data<p>There are a wide variety of clockless circuits that each make their own timing assumptions. QDI is the most paranoid, making the fewest timing assumptions. Bundled-data is the least paranoid (its effectively clock-gating).<p>A clockless pipeline is always going to be slower than a clocked one and requires about 2x the area. However, clockless logic is way more flexible, letting you avoid unnecessary computation. Overall, this can mean significantly higher throughput and lower energy, but getting those benefits requires <i>very</i> careful design and completely different computer architectures.<p>Most of the VLSI industry is woefully uneducated in clockless circuit design and the tools are terribly lacking. I&#x27;ve seen many projects go by that make a synchronous architecture clockless, and they have always resulted in worse performance.<p>What this means is that it would take billions of dollars for current VLSI companies to retool, and doing so would only give them a one-time benefit. So, you probably won&#x27;t see clockless processors from any of the big-name companies any time soon. What they seem to be doing right now is buying asynchronous start-ups and shutting them down.<p>As of the 90nm technology node, its not possible to be switching all of the transistors on chip without lighting a fire. This mean that the 2x area requirement is not much of a problem since a well-designed clockless circuit only needs to switch 25-50% of them at any given time. Also since 90nm, switching frequencies seem to have plateaued with a max of around 10 GHz and typical at around 3 GHz. When minimally sized, simple clockless pipelines (WCHB) can get at most 4 GHz and more complex logic tends to get around 2 GHz (for 28nm technology). Leakage current has become more of a problem, but it&#x27;s a problem for everyone.<p>There is a horribly dense wikipedia page on QDI, but it has links to a bunch of other resources if you are curious.
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lizknope大约 6 年前
I&#x27;ve been designing semiconductors for 23 years. This article is 17 years old and I haven&#x27;t seen any clockless designs in my professional experience in all of that time.<p>About 1&#x2F;3 to 1&#x2F;2 the power usage is leakage and I don&#x27;t see how a clockless design will help that. We dynamically lower the voltage and have power islands for unused or lesser used portions.<p>nbingham makes a great point about the tools. We have invested billions of dollars in tool flows. We are not going to throw that away until we see some proof that clockless designs are better in some measurable ways.
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snazz大约 6 年前
The GA144, a 144-processor stack machine that’s insanely energy efficient, is clockless: <a href="http:&#x2F;&#x2F;www.greenarraychips.com&#x2F;home&#x2F;documents&#x2F;index.html#architecture" rel="nofollow">http:&#x2F;&#x2F;www.greenarraychips.com&#x2F;home&#x2F;documents&#x2F;index.html#arc...</a><p>I haven’t seen any legitimate uses for it yet, but it’s very cool.
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EdwardCoffin大约 6 年前
Previous discussion from almost exactly three years ago [1]. From my comment that time [2] here is the link to archive.org&#x27;s copy of Sutherland&#x27;s FLEET project [3]<p>[1] <a href="https:&#x2F;&#x2F;news.ycombinator.com&#x2F;item?id=11425533" rel="nofollow">https:&#x2F;&#x2F;news.ycombinator.com&#x2F;item?id=11425533</a><p>[2] <a href="https:&#x2F;&#x2F;news.ycombinator.com&#x2F;item?id=11426825" rel="nofollow">https:&#x2F;&#x2F;news.ycombinator.com&#x2F;item?id=11426825</a><p>[3] <a href="https:&#x2F;&#x2F;web.archive.org&#x2F;web&#x2F;20120227072220&#x2F;http:&#x2F;&#x2F;fleet.cs.berkeley.edu&#x2F;" rel="nofollow">https:&#x2F;&#x2F;web.archive.org&#x2F;web&#x2F;20120227072220&#x2F;http:&#x2F;&#x2F;fleet.cs.b...</a>
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