TRRespass: Rowhammer against DDR4

IIRC, there was a proposal some time ago to use performance counters to detect a rowhammer attempt (high number of cache misses) and stop it (by pausing the offending process until the DRAM refresh can catch up). Did anything come out of it?

I wish we could get rid of this dependency on the natural world that computers seem to have. Sadly I cant of a way to implement computers outside of reality and have some safe interface to them.

Theoretically, if we accepted lower performance, could we design our hardware and software to actually be secure? The number of exploits over the last two years is making my head spin

ECC should be standard and mandatory at this point.

How expensive would 16 GiB of refress-less "4 nm" SRAM placed on the CPU package flip-chip style be?

Time yet to add support to encrypt memory transparently in the DRAM controller?

might want to merge this with <a href="https:&#x2F;&#x2F;news.ycombinator.com&#x2F;item?id=22547324" rel="nofollow">https:&#x2F;&#x2F;news.ycombinator.com&#x2F;item?id=22547324</a>