ULX3S: Hackable FPGA that runs Linux on RISC-V

Also newsworthy: Lattice drops recent EULA clause forbidding fpga bitstream reverse engineering <a href="https:&#x2F;&#x2F;hackaday.com&#x2F;2020&#x2F;06&#x2F;06&#x2F;lattice-drops-eula-clause-forbidding-fpga-bitstream-reverse-engineering&#x2F;" rel="nofollow">https:&#x2F;&#x2F;hackaday.com&#x2F;2020&#x2F;06&#x2F;06&#x2F;lattice-drops-eula-clause-fo...</a> therefore 2020 could be a milestone for open FPGA toolchains!

Is there any published rationale for the RISC-V instruction encoding?<p>A few months back I set out to write a software emulator of RISC-V for fun. I expected the instruction set encoding to lend itself well to a very simple implementation, eg. something you could decode in 5-10 lines of C plus some tables.<p>But the instruction encoding is much more irregular than I expected: <a href="https:&#x2F;&#x2F;github.com&#x2F;ucb-bar&#x2F;riscv-sodor&#x2F;blob&#x2F;master&#x2F;src&#x2F;common&#x2F;instructions.scala" rel="nofollow">https:&#x2F;&#x2F;github.com&#x2F;ucb-bar&#x2F;riscv-sodor&#x2F;blob&#x2F;master&#x2F;src&#x2F;commo...</a><p>In particular:<p><pre><code> - The bit patterns allocated to the simplest instructions (eg. rv32i) seem random. Why not allocate starting from zero to allow dense jump tables? - I can&#x27;t make any sense of the groupings. A bunch of instructions have 0b1100011 in the lowest bits, do these instructions have something in common? </code></pre> I assume there is some rhyme and reason to all this? Where is this explained?

The ULX3S is great! I built myself an early prototype a year ago, and have used it every so often for occasional hacks. It has since evolved to be a first-class citizen in a number of projects and frameworks (LiteX, including LiteDRAM), which makes it great to get started with.<p>Also worth noting, that you can use a fully open source flow (Yoys + nextpnr + prjtrellis) for this FPGA family. Here&#x27;s a repository I made that shows a basic blinky for an ULX3S: <a href="https:&#x2F;&#x2F;github.com&#x2F;q3k&#x2F;ulx3s-foss-blinky&#x2F;" rel="nofollow">https:&#x2F;&#x2F;github.com&#x2F;q3k&#x2F;ulx3s-foss-blinky&#x2F;</a>

Where&#x27;s the article? I see mostly a bunch of loosely related bullet points.<p>Edit: After a lot of back and forth, perhaps this is a good intro: <a href="https:&#x2F;&#x2F;hackaday.com&#x2F;2019&#x2F;01&#x2F;14&#x2F;ulx3s-an-open-source-lattice-ecp5-fpga-pcb&#x2F;" rel="nofollow">https:&#x2F;&#x2F;hackaday.com&#x2F;2019&#x2F;01&#x2F;14&#x2F;ulx3s-an-open-source-lattice...</a>

Layman question: how many years before we get RISC-V desktops or Raspberry Pi like computers?

Remember there is a lecture by a guy who demo on a game emulation program. Wait for it since.<p>Just placed an order : <a href="https:&#x2F;&#x2F;www.crowdsupply.com&#x2F;radiona&#x2F;ulx3s" rel="nofollow">https:&#x2F;&#x2F;www.crowdsupply.com&#x2F;radiona&#x2F;ulx3s</a>

Can anyone comment on how this compares to the popular Terasic DE10-Nano used for the MiSTer project? The price point is around the same and I see they note running video game cores as a market for this device, but I have absolutely no clue how to reasonably compare FPGAs.<p>From my rudimentary understanding it looks like this doesn&#x27;t have a hard CPU and has a smaller FPGA, so I&#x27;m guessing we have a fair bit of &quot;open hardware tax&quot; at play here too.

Cool! It also does Oberon, MicroPython and Basic.

Is it any better than Artix-7 XC7A100T or XC7A35T boards from Aliexpress(search QMTECH, they sell 100K board for ~$100)?

very impressive project, its a good time to get into fpga projects

How does it compare to the Arty A7 for $129?

Theoretically every fpga is hackable

The dollar sign comes before the number, not after it.<p>$150

2x more resources compared to $30 <a href="https:&#x2F;&#x2F;github.com&#x2F;q3k&#x2F;chubby75" rel="nofollow">https:&#x2F;&#x2F;github.com&#x2F;q3k&#x2F;chubby75</a> at 5x the price