Ariane RISC-V CPU – An open source CPU capable of booting Linux

So I&#x27;ve had the itch to get a 64-bit RISC-V board of some sort. For reasons I won&#x27;t get into, I&#x27;m not so interested in the 32-bit version.<p>The prices for the Genesys 2 Kintex-7 are $1000 USD at Digikey, which is way too much to spend on a hobby. I suppose I could try to port the FPGA code to a cheaper platform, but I&#x27;m no expert on that sort of development.<p>Arguably, I&#x27;m not an expert on operating systems development either...<p>On the other end of the spectrum, There is this Canaan Kendryte K210 chip, which is a dual-core 64-bit RISC-V SoC, but only has 8MiBytes of on-chip SRAM, with no provision for SDRAM. An RTOS is of course the straight-forward choice for that, though people are apparently able to run a very slim Linux kernel on it as well. You can get various boards from Seeed Studio for $30 USD or less.<p>Is there something else that is a reasonable price? Less than $100 USD? Yes, I know, qemu is free.

I love that the controller symbol is a toilet, because on a miss-predict it does a &quot;flush&quot;.

Could someone break down the significance of this for those of us who are less hardware-acquainted? Does this represent the cutting edge of RISC-V CPU design? And how difficult would it to implement this design properly instead of simply emulating it with an FPGA?

RISC-V could be a pretty good ISA, if only it came with a popcount instruction. Given popcount, it is easy to compose a whole range of other essential operations with just one or two more instructions. Without, you are stuck running two dozen instructions just to get to the first step.<p>Is the RISC-V evolutionary process capable of processing small-sized, incremental improvements? Or are only big &quot;extension&quot; instruction families even possible?

Cool. No register renaming but scoreboared issue means it&#x27;s still weakly out of order. It seems to be grabbing the instruction stream in 32 bit chunks but I wonder if it can decode two compressed instructions in a single clock cycle?

What’s so attractive in RISC-V compared to, say, ARM or MIPS? Is it just the license?

Looks like it just shares a name with the spacecraft but isn&#x27;t related?