What is your background and what do you want out of it?<p>IMO a good way to start is by buying an FPGA development kit such as <a href="https://canada.newark.com/terasic-technologies/p0037/dev-board-altera-de0-board/dp/47W2946?gclid=Cj0KCQjw8rT8BRCbARIsALWiOvQuc2amPwAegt4gC_quf3nb_Dfa-DzEArrpH8PbZ7N-q-5ifxHHO2caAspUEALw_wcB&mckv=sHPnGZhCU_dc|pcrid|436284254564|plid||kword||match||slid||product|47W2946|pgrid|106725849772|ptaid|pla-931785691809|&CMP=KNC-GCA-GEN-Shopping-NewStructure-Embedded-Computers-Education-MakerBoards" rel="nofollow">https://canada.newark.com/terasic-technologies/p0037/dev-boa...</a> which has a bunch of I/O and cool things to do with.<p>The FPGA kit will come with some golden designs and instructions to download and install the EDA software. Feel comfortable with the FPGA software and make some leds blink..<p>Now you're in a position that you can download a hardware design to the FPGA and use the pins!<p>RTL Hardware Design Using VHDL: Coding for Efficiency, Portability, and Scalability is an amazing book for learning how to do RTL logic, buy the book, read, execute the examples!<p>Now you have a kit and you know RTL! Next you can learn the algorithms you want and implement them!<p>My workflow used to be something like:<p>1. Implemented an algorithm using fixed point math in Matlab (or Octave)<p>2. Develop the VHDL equivalent to (1), test with something like ModelSim<p>3. Generate the RTL with the EDA software and download to the board!<p>To test step (3) it really depends what your algorithm is.. if you can easily control your inputs and outputs through a computer connected to the FPGA then it is a good way to go about it! You might also want to develop a RTL module to connect to your design and generate the inputs / see the output, or buy some expensive hardware to verify that your design is working as intended.<p>Hopefully that is helpful.. it is a vast field and there are many algorithms, FPGA sizes and etc. A kit like the one I sent should be enough to go from 0 to a decent size design...
The other comment about a kit is a good suggestion. FPGA cloud instances are also an option.<p>Register Transfer Level (RTL) development generally has less pleasant tooling and a much longer feedback cycle than software development. So expect some friction there.<p>Also, for the algorithms part, you might have something in software that isn’t a great match to hardware and will need some re-architecting. Sorting is a good example of this. Check out “sorting networks” for a popular way of accomplishing sorting in hardware.<p>I did a master’s thesis on transitioning a graph inference algorithm into an FPGA implementation.
Send me an email if you have any specific questions.