Awesome! The current a transistor can put out is porportional to the width over the length and chip designers usually want wide transistors[1], but wide transistors take up space which causes more line capacitance. This innovation will let people put more, wider transistors in a given area which will both increase the current they're putting out and decrease the capacitance they're fighting against, leading to higher frequencies[2].<p>[1] Wider transistors also cause more capacitance for the other transistors that are driving them, but for most modern designs this is smaller than line capacitance.<p>[2] Having transistors closer together can also help overcome speed-of-light delay. This can be important in caches.<p>EDIT: Also, some stuff I didn't notice until reading the Anandtech article is that the thinness of the silicon will give you the same artificial limitation of the depletion region that SOI does, leading to the same accelerated inversion. Oh, and better isolation from the base too. I don't think that I can explain that succinctly for non-EEs so go read Wikipedia on MOSFETs if you're interested.