Not that this will ever matter for someone who isn't a circuit designer, but the "optimal" solution for the latch is actually really bad.<p>If you use a "select" block (which should really be called "mux") and tie the output to the input, you create a race condition. If the data input is 1, and you change set from 1 to 0, the output can actually glitch to 0 for a very short period of time, which is a big no-no. (If you draw the equivalent circuit out with just nand gates and assume they all have some delay between input and output, you'll see why).<p>A safer solution would be to cross couple two nand gates into an SR latch [0], use another two nand gates to control the Set and Reset signals, and an inverter to create NOT(data).<p>Of course in reality, a latch is usually custom built out of transistors rather than logic gates, but there are some cases where I've used logic-gate-latches to make things easier.<p></pedanticism><p>[0] <a href="http://electronics-course.com/sr-nand-latch" rel="nofollow">http://electronics-course.com/sr-nand-latch</a>