<a href="http://www.fpga4fun.com/" rel="nofollow">http://www.fpga4fun.com/</a> is a great starting place. FPGA tool chains have a pretty brutal learning curve, but if you have the hardware mindset and can deal with waveforms, they're not that hard. The worst part of the learning curve I found was the subtle issues that are different between simulation and synthesis, along with outright bugs in some of the simulation libraries (Xilinx, I'm looking at you - your simulated FIFOs are buggy!). Sticking to particular coding styles can avoid this (avoid asynchronous resets like the plague), but there is not as much material available on this topic for Verilog and VHDL as with software programming languages. Getting data into and out of a chip is where a lot of these problems crop up. Xilinx's SERDES blocks are absolutely insane to get working the first time one tries. The Microsemi Polarfire was ridiculously easy compared to that. Gigabit ethernet and GMII have weird timing issues that you have to be aware of (ODELAY on the Spartan 6 is needed to satisfy the Marvell PHYs, while other boards with a National Semiconductor PHY don't care about that 1ns).<p>Maybe it's a bit harder than I admit now that I think about all the battle scars from fooling around with FGPAs over the last 12 years...