Conway's Game of Life on FPGA

I&#x27;ve been working with FPGAs for years (in hobby, at work I&#x27;m a mere &quot;user&quot; of them), and it always baffled me how poorly matched the chosen imperative paradigm of Verilog and VHDL is to them.<p>I think the idea was to make it look &quot;familiar&quot; to engineers by looking like C (Verilog) or Ada (VHDL). But FPGAs are nothing like CPUs, and what you end up with instead is an unfitting language where you use a whole lot of &quot;common constructs&quot;, knowing how they will be synthesized into hardware. And worse: Practically no good way to do abstraction.<p>Functional languages are a much, much better match, because that&#x27;s what FPGAs are: Combining functions together. This works on higher orders as well, and it works well with polymorphism!<p>So privately at least, for anything substantial I&#x27;ve since been using Clash, which is essentially a Haskell subset translated to Verilog or VHDL: <a href="https:&#x2F;&#x2F;clash-lang.org" rel="nofollow">https:&#x2F;&#x2F;clash-lang.org</a><p>The learning curve is steep, it definitely helped that I was already proficient in Haskell. But then the code is so enormously concise and modular, and I now have a small library of abstractions that I can just reuse (for example, adding AXI4 to my designs). It&#x27;s a joy.

Funny, it looks like the practical work we had to do in our CS master class &quot;advanced digital systems design&quot;, something like 20 years ago, on a nowadays archaic XC4013 FPGA... (including the VGA part).

Very nice! I would quibble with this bit: <i>Verilog initially focused on describing the hardware–very close to what could be expressed by conventional schematic–and later added general-purpose programming elements to create more complex components.</i><p>The concept here is &#x27;inference&#x27; or &#x27;synthesis&#x27; and it is the fundamental difference between and HDL and an imperative programming language. When you write general purpose statements in an HDL, the tools have to infer what sort of hardware would give you that behavior, and in a funny twist, the more you lean on high level language features the more likely you are to run into something that cannot be synthesized into hardware gates. Perfectly valid HDL with no valid solution!

I implemented Conway’s game of life in VHDL to run on a Xilinx FPGA board in my digital electronics class in college - interestingly, I think the hardest part was actually the HDMI driving.

I wonder how this would compare to a GPU accelerated GoL.

Very nice! Have you thought about making a clock-free version of this design?

I love that Conway published a request for proof that infinite games existed, or something to that effect. And the proof turned out to be known as a Gun structure (iirc). A Gun is essentially a starting condition that leads to new projectiles continuously getting launched into the world, thus creating infinite (and non repeating?) games.

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