The problem with recreating the original Project Oberon system hardware on a current FPGA board is that Prof. Wirth's original design for the Xilinx Spartan 3 starter kit board (<a href="https://reference.digilentinc.com/spartan-3/spartan-3" rel="nofollow">https://reference.digilentinc.com/spartan-3/spartan-3</a>) relied on the fact that this board had 1 MB of fast, 32 bit wide, asynchronous SRAM, which is easy to handle. Thus, the CPU clocked at 25 MHz didn't require a cache and even had cycles to spare for the framebuffer accesses.<p>The OberonStation board replicated this design by using two 16-bit wide SRAMs. All other current boards using SRAM only have a single 16-bit wide SRAM, so all accesses to machine words such as the RISC5 instructions would take two cycles; often, the RAM is also too small, e.g. the BlackIce (<a href="https://mystorm.uk" rel="nofollow">https://mystorm.uk</a>) has only 512 kB.<p>Most of the boards on the market today have SRAM or DDR RAM, which makes controlling the external memory much more complex and requires significant changes to the nice and simple Project Oberon hardware. There are ports using SDRAM, e.g. for the ulx3s (<a href="https://radiona.org/ulx3s/" rel="nofollow">https://radiona.org/ulx3s/</a>, <a href="https://github.com/emard/oberon" rel="nofollow">https://github.com/emard/oberon</a>) or FleaFPGA and Papilio Pro (<a href="https://opencores.org/projects/oberon_sdram" rel="nofollow">https://opencores.org/projects/oberon_sdram</a>).<p>On a really large FPGA, you could get by using on-chip block RAM only, but FPGAs with 1 MB of block RAM are still quite expensive...