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Libre-SoC 180nm Power ISA v3.0 ASIC Submitted to IMEC MPW

91 点作者 lkcl将近 4 年前

9 条评论

cjsplat将近 4 年前
For SW type people ...<p>GCC&#x27;s impact was possible because it was (with GAS - the assembler) 100% feasible to have an open source toolchain. Yes more software was necessary for a complete system (linker, libc, etc), but GCC made it possible to build from the ground floor up.<p>Also, yes, the initial GCC was worse than any proprietary decent tool chain at the time, but it got better and better because each improvement built on all the earlier open sourced efforts.<p>Think about how hard Linux kernel development would have been if it had to rely on different proprietary tool chains for every target architecture (and possibly chip version).<p>Hardware definition languages (Verilog&#x2F;VHDL, etc) enable high level chip design like high level programming languages, but making the physical chip requires a PDK (process design kit) that encodes how each critical silicon feature is built.<p>So a chip built for TSMC 28nm contains TSMC proprietary material and is essentially unportable. It can take several years to move a major chip from one foundry to another (or even a shrink at the same foundry), and the proprietary tool chains preclude a development process that can incrementally improve portability.<p>This announcement is a a major step toward a similar foundation being available for silicon design. It is very important that it is a large complex chip, rather than just a research development vehicle.<p>[disclaimer - past life as OpenPOWER participant]
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dragontamer将近 4 年前
A fully open source chip, from Verilog to Fabrication is cool!<p>It may be 180nm (1999-era technology), but that&#x27;s still hugely important. The world of semiconductor design is incredibly closed source and secretive.
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marcodiego将近 4 年前
This is a very important step. I don&#x27;t understand how this is not on the first page. Maybe a more click-baity title is needed?
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KirillPanov将近 4 年前
&gt; Symbolic (ghost) versions of FlexLib allowed Libre-SOC developers to not have to sign a Foundry NDA during the development of the ASIC Layout<p>In other words, this chip isn&#x27;t even remotely open-source.<p>What they sent to the foundry isn&#x27;t the &quot;ghost cells&quot; (which don&#x27;t have transistors in them and therefore don&#x27;t work).<p>This fails the most basic requirements of being open source.
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phendrenad2将近 4 年前
I can&#x27;t wait to see the Vulkan implementation for this. Apparently it should be somewhat hardware-accelerated due to the vector capabilities of the core?
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gnufx将近 4 年前
Interesting as this is, I&#x27;ll look forward to version two, to see how the vector processing works.
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Narishma将近 4 年前
I didn&#x27;t see any specs for this SoC in the article, did I miss it?
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vfclists将近 4 年前
What does this mean to noobs like me?
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fithisux将近 4 年前
Congratulations.
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