Apple M1 Max die has an entire hidden section on the bottom

This is the first time someone at least make some sense of the whole M1 Max Chiplet theory &#x2F; hypothesis. That there is an interconnect ready. Unlike all previous comments there people suggest they magically stack 2 - 4 SoC together.<p>The TSMC MCM interposer size is the same as 4x M1 Max Die Size. Should they choose that route at a potential of 500W+ TDP Design.<p>Still doesn&#x27;t solve NUMA issue though. Along with GPU access. This is basically the same design as Zen 1. It was the whole reason why there is an IOD in the middle with Zen 2 and above. And I hope Apple has something clever to show the word why Zen 1 failed and they succeed.<p>On the GPU I am thinking something from PowerVR [1] if it works as advertise. I just wish we could get more information soon.<p>[1] <a href="https:&#x2F;&#x2F;www.anandtech.com&#x2F;print&#x2F;16155&#x2F;imagination-announces-bseries-gpu-ip-scaling-up-with-multigpu" rel="nofollow">https:&#x2F;&#x2F;www.anandtech.com&#x2F;print&#x2F;16155&#x2F;imagination-announces-...</a>

Subtitled: Person tweets rumour with zero evidence and becomes runaway tweet storm - oh wait, that isn’t what happened

Looks like a provision for some kind of EMIB like interconnect.