Compiling code into silicon

Pretty neat, a python tool that converts Verilog to an IC layout so that you can make your own custom SOC (assuming you have a substantial budget to pay for fab).<p>Since it&#x27;s not clearly stated on the front page, I had to go digging to figure out what processes it supports. Looks like FreePDK45, which is &quot;an open-source generic process design kit (PDK) (i.e., does not correspond to any real process and cannot be fabricated)&quot; [0], ASAP7 &quot;Warning Work in progress (not ready for use)&quot; [1] and Skywater130 which &quot;As of May 2020, this repository is targeting the SKY130 process node. If the SKY130 process node release is successful then in the future more advanced technology nodes may become available.&quot; [2] The floorplanner supports their ZeroSOC [3] which I guess is based on TitanSOC [4]<p>If this sounds negative, it&#x27;s not, I just couldn&#x27;t figure out what processes this was intended for without digging. ASAP7 is Arm and NCSU, and Skywater130 is Skywater and Google.<p>[0] <a href="https:&#x2F;&#x2F;github.com&#x2F;mflowgen&#x2F;freepdk-45nm" rel="nofollow">https:&#x2F;&#x2F;github.com&#x2F;mflowgen&#x2F;freepdk-45nm</a> [1] <a href="https:&#x2F;&#x2F;docs.siliconcompiler.com&#x2F;en&#x2F;latest&#x2F;reference_manual&#x2F;pdks.html" rel="nofollow">https:&#x2F;&#x2F;docs.siliconcompiler.com&#x2F;en&#x2F;latest&#x2F;reference_manual&#x2F;...</a> [2] <a href="https:&#x2F;&#x2F;github.com&#x2F;google&#x2F;skywater-pdk" rel="nofollow">https:&#x2F;&#x2F;github.com&#x2F;google&#x2F;skywater-pdk</a> [3] <a href="https:&#x2F;&#x2F;github.com&#x2F;siliconcompiler&#x2F;zerosoc" rel="nofollow">https:&#x2F;&#x2F;github.com&#x2F;siliconcompiler&#x2F;zerosoc</a> [4] <a href="https:&#x2F;&#x2F;github.com&#x2F;lowrisc&#x2F;opentitan" rel="nofollow">https:&#x2F;&#x2F;github.com&#x2F;lowrisc&#x2F;opentitan</a>

My favourite approach for this is &quot;compiling to categories&quot; <a href="http:&#x2F;&#x2F;conal.net&#x2F;papers&#x2F;compiling-to-categories" rel="nofollow">http:&#x2F;&#x2F;conal.net&#x2F;papers&#x2F;compiling-to-categories</a><p>Essentially: lambda calculus (and hence functional programming) can be given many different interpretations; whilst we usually interpret it as a computer program describing some result value, we can also interpret it as a circuit description, and turn it directly into hardware.

why is this stuff almost always Python-based?<p>Have we not learned? Python is a fine language, but it is dynamically type checked, and not compiled to binaries. There is so much evidence all around us that statically type-checked, compiled languages produce better, more performant code, and allow for application stability and longevity much more easily.<p>I get that Python may be your favorite language, and that&#x27;s fine, and that alone doesn&#x27;t immediately qualify it as a good choice for anything, if you&#x27;re being objective.

&gt; Process scaling is coming to an end and it is a social imperative that we find a new path to extend the Moore&#x27;s Law exponential.<p>... is it? Are our human rights at risk here? This sentence feels weird.

&gt; ... Compiling simple programs into silicon should be like using llvm or gcc: fast, automated, and accessible.<p>Some benchmarks would have been helpful. What kind of performance gain are there to make?

So the purpose of this is basically to design an ASIC in code? I’m skeptical about “extreme silicon specialization” being the “most viable” replacement to Moore’s law. Has that not already been the case since forever? The compute intensive things has already been moved onto specialized chips ala GPUs, TPUs, etc.

I wonder why the homepage doesn&#x27;t mention FPGA or ASIC once?

This reminds me very much of edalize[1], which does something very similar.<p>[1]: <a href="https:&#x2F;&#x2F;github.com&#x2F;olofk&#x2F;edalize" rel="nofollow">https:&#x2F;&#x2F;github.com&#x2F;olofk&#x2F;edalize</a>

Personally I have fond memories of MyHDL [0], which may be seen as another &quot;code-to-silicon&quot; converter (or at least as the first step of a code-to-silicon workflow). I used it only briefly, and on a school project that had surprisingly little to do with actual hardware design [1], but it really felt &quot;Pythonic&quot; in the best possible way.<p>[0]: <a href="https:&#x2F;&#x2F;www.myhdl.org&#x2F;" rel="nofollow">https:&#x2F;&#x2F;www.myhdl.org&#x2F;</a><p>[1]: <a href="https:&#x2F;&#x2F;github.com&#x2F;lou1306&#x2F;gssi&#x2F;tree&#x2F;master&#x2F;2pc" rel="nofollow">https:&#x2F;&#x2F;github.com&#x2F;lou1306&#x2F;gssi&#x2F;tree&#x2F;master&#x2F;2pc</a>

Hmm… I thought that this was a treatment of the classic “silicon compiler”[0]. It basically is, with Python, as opposed to the usual; which is generally subtypes of C or C++.<p>That said, this is definitely a great way to handle some types of product development.<p>It’s just that, once it becomes hardware, different rules apply to pretty much everything else in the project.<p>[0] <a href="https:&#x2F;&#x2F;en.m.wikipedia.org&#x2F;wiki&#x2F;Silicon_compiler" rel="nofollow">https:&#x2F;&#x2F;en.m.wikipedia.org&#x2F;wiki&#x2F;Silicon_compiler</a>

It&#x27;s hard to say from the webpage, but this looks actually like a (frontend for a) place-and-route tool. No idea why to reinvent the terminology.

I was hoping, like others in this thread, to see something that takes HLL code and outputs a ASIC design. Of course it would have to be limited in the type of code it can take.<p>It is similar to programming FPGAs. Are there applications that use FPGAs running close to CPUs in the cloud? Or CPUs are fast enough and much cheaper than using FPGAs.

When I’ve inquired about this in the past I was told that relatively few programs compiled to silicon would outperform the same program running on a generalized chip (e.g., x86). Is this not the case?

Seems similar to the Chisel compiler for RISC-V:<p><a href="https:&#x2F;&#x2F;github.com&#x2F;chipsalliance&#x2F;chisel3" rel="nofollow">https:&#x2F;&#x2F;github.com&#x2F;chipsalliance&#x2F;chisel3</a>

Is this for ASICs or permanent SOC type solutions?

I&#x27;m having trouble understanding what this actually does. I think it wraps existing open source ASIC tools?

So much python here, but it gets the job done.

How is this different from FPGA?

How is this different to HLS