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Camel: CXL-based memory disaggregation framework

31 点作者 blopeur大约 3 年前

1 comment

rektide大约 3 年前
Worth clicking for just the image of the memory-board they&#x27;ve built. Unlike most pcb&#x27;s, it&#x27;s stark &amp; open, hardly a passive component on it. Really wild to see so much open boardspace. They have 8 dimms here. I suspect it&#x27;s basically just an FPGA acting as a CXL memory controller, but perhaps there&#x27;s more.<p>They compare themselves versus RDMA over Infiniband (56Gbps) which makes sense as it&#x27;s the competitor. It&#x27;s not clear to me whether they are using their CXL switch in their tests, or whether the CXL memory is directly attached; I&#x27;d be curious to know what the performance hit is for switching. But the idea of massive fan out memory is definitely compelling!<p>Medium term, I imagine we&#x27;ll be seeing variants of stuff like this with HBM stacks onboard. See the recent UCIe chiplets alliance[1], with AMD, Intel, TSMC, Samsung, others. To tie it back to my first comment, this would just be a modest modern microminaturization of this wide open sparsely-populated huge PCB... just put this whole thing on chip. It&#x27;d make a very large (capacity), very small (footprint) memory module.<p>It&#x27;s unsurprising that this company is claiming some patents over this technology even in the press brief. Hopefully the core ideas of CXL are allowed to germinate &amp; grow, without the ecosystem immediately becoming IP overencumbered.<p>[1] <a href="https:&#x2F;&#x2F;www.servethehome.com&#x2F;universal-chiplet-interconnect-express-ucie-1-0-launched&#x2F;" rel="nofollow">https:&#x2F;&#x2F;www.servethehome.com&#x2F;universal-chiplet-interconnect-...</a> <a href="https:&#x2F;&#x2F;news.ycombinator.com&#x2F;item?id=30538809" rel="nofollow">https:&#x2F;&#x2F;news.ycombinator.com&#x2F;item?id=30538809</a> (92 points, 12 days, 26 comments)