Making open source hardware design a reality

Whilst open source hardware work goes back a fair way, I feel we&#x27;re really at a turning point where it can become a serious force within the hardware world (think late 80s&#x2F;early 90s in software terms, Linux and GCC emerging and beginning to find their feet). There&#x27;s lots of interesting developments in tooling plus significant open hardware projects on-going.<p>I shall take the opportunity to plug OpenTitan: <a href="https:&#x2F;&#x2F;github.com&#x2F;lowRISC&#x2F;opentitan" rel="nofollow">https:&#x2F;&#x2F;github.com&#x2F;lowRISC&#x2F;opentitan</a><p>It&#x27;s an open source root of trust being developed collaboratively by multiple companies such as lowRISC (who I work for), Google, Western Digital and Seagate amongst others. We&#x27;ve been rather quiet on the PR front but there&#x27;s a lot of engineering work happening and other exciting things we can&#x27;t yet make public.<p>Whilst there&#x27;s some things we have to keep closed (generally relating to ASIC design kits and things like Flash and memory IP) the vast majority of the RTL, documentation and software is open. Plus we&#x27;re doing development in the open, the public repo is our live development repo. We&#x27;re not developing it in private then just opening the end product.

Hey, it&#x27;s the man behind the parallela chip (and the 100$ sbc)<p>He worked hard to deliver his kickstarter. Happy to see him still active in the field.

Related: I would recommend people look into cocotb and uvm-python which let you do verification of SystemVerilog designs in Python. This has been a game changer for me, and it is much more productive than writing tests in SystemVerilog in my experience.

Although I don&#x27;t (yet) own a real FPGA, I recently started to learn Verilog and wanted to see if I could program one using only open-source tools. My first impression is that the tooling is too fragmented and the documentation is lacking. I still don&#x27;t fully understand the relationships between the major projects - F4PGA (is this the same as SymbiFlow?), VTR, yosys, ABC.<p>Ultimately I figured out how to use yosys+nextpnr so if I ever decide to dive deeper into the FPGA world, I will probably get an iCE40.<p>Also, is there an open-source tool for post-routing simulation? AFAIK this requires SDF annotation support which iverilog doesn&#x27;t have.

I&#x27;m less interested in design than I am in implementation<p>Anyone want to donate a fab to a poor hn user? lol

I mentioned Libre-SOC under another item; their tools are listed at <a href="https:&#x2F;&#x2F;libre-soc.org&#x2F;HDL_workflow&#x2F;" rel="nofollow">https:&#x2F;&#x2F;libre-soc.org&#x2F;HDL_workflow&#x2F;</a>

While yosys and nextpnr are great and work for simple and low assurance designs I understand why they don&#x27;t take over in industry. Main reason is just that basic functionality is not there yet. Take for example an asynchronous FIFO used for clock crossing. Used widely in industry. Yet it&#x27;s not supported because there is no way to specify the required timing constraints. Of course you can still synthesize your design but whether it works or not is just luck.

Is there any alternative for Cadence Virtuoso Layout Suite?

Nice list! Bookmarked. How comes not any board or open hardware design platform like Arduino or any sparkfun&#x2F;nodemcu&#x2F;etc are listed? Not even based on the platform they are based?

The list seems to include only projects with a github page?