I think most HN users are not familiar with the pre-silicon verif environment, and so, don’t understand what a testbench is. I am fairly familiar with it, and I think I debugged testbench issues at some point, and I don’t really know what it is either.<p>But I’ll give it a shot, more informed users please correct me.<p>The testbench is a wrapper that turns command line options into binary file arrangements consumed by the simulator. For example, you could have a flag like -FORCE_ALL_CLOCKS_ON. The simulator software doesn’t think on this level, you actually need some piece of verilog, maybe compiled into some sort of patch, that makes some enable bits do nothing.<p>The testbench is a wrapper that determines if a test has passed or failed. There may be complex criteria to determine this, mostly by parsing logs, but it could hook in to the simulator in a more sophisticated way too.<p>The testbench is a wrapper that can fuse multiple simulators, so if your core is in FPGA but you have an Ethernet model in high level software (probably SystemVerilog?) you need a shim to get them talking.<p>The testbench is what you execute at the command line when you want to execute your tests.<p>The testbench is probably more than that. Or maybe less.