Learning Verilog and FPGA

For me the key to making everything understandable was adding more constraints to keep myself out of trouble. Everything is a finite state machine, exclusively non-blocking assignments, always loops use the rising edge of the clock signal only.

I tried Verilog at first but found myself liking vhdl quite a lot more. It just fit my mental model better and helped avoid some really silly errors I kept making as a beginner.<p>I could probably pick up Verilog now a bit quicker, I’d jump straight to system Verilog though if I did.

Greg Stitt shares amazing training materials freely (he uses them for his undergraduate and graduate courses). His synthesizable HDL methods are really empowering for beginner developers<p><a href="https:&#x2F;&#x2F;github.com&#x2F;ARC-Lab-UF&#x2F;vhdl-tutorial">https:&#x2F;&#x2F;github.com&#x2F;ARC-Lab-UF&#x2F;vhdl-tutorial</a><p><a href="http:&#x2F;&#x2F;www.gstitt.ece.ufl.edu&#x2F;" rel="nofollow">http:&#x2F;&#x2F;www.gstitt.ece.ufl.edu&#x2F;</a>

In my case, building a miner and computation accelerator with FPGA boards really help me understanding the applications of FPGA. Though I have started learning HDL languages to build digital circuits, to me, that&#x27; not such an interesting subject, however, accelerated computing with FPGA had been very interesting experience.

I started playing with FPGAs and HDLs a couple years ago with no hardware design background (I&#x27;m mostly a software architect&#x2F;engineer) and in the end found that a &quot;higher-level&quot; HDL suited me better.<p>I chose Chisel (<a href="https:&#x2F;&#x2F;www.chisel-lang.org&#x2F;" rel="nofollow">https:&#x2F;&#x2F;www.chisel-lang.org&#x2F;</a>) an HDL based on Scala (technically a Scala DSL) which can provide many facilities to hardware generation.<p>I&#x27;d highly advise looking into it although also knowing Verilog helps a lot.

Is there an FPGA with a totally Free and Open toolkit yet?

In the past I worked on a project with a soft CPU (Altera NIOS) with some custom Verilog written for glue logic. It was nice because the NIOS is just like a generic microcontroller so it&#x27;s painless to try out some different Verilog blocks without having to interface an external micro. The toolchain is monstrous though, although free versions are available it&#x27;s just a huge clunker to work with.