The future of computers: 3D chip stacking

Xilinx's Vertex 7 FPGA uses a stacked design for the interconnects. The FPGA logic is all 28nm, but sitting under it is a completely passive 65nm interconnect layer.<p><a href="http://www.xilinx.com/products/technology/stacked-silicon-interconnect/index.htm" rel="nofollow">http://www.xilinx.com/products/technology/stacked-silicon-in...</a>

&#62; <i>"chip stacking obviously works in synergy with Intel’s 3D FinFETs — though curiously there is no sign of TSV on Intel’s roadmap"</i><p>Wouldn't chip stacking exacerbate heat dissipation issues? It seems to me that desktop chips would stand to gain far less from this approach, so why should it be surprising that Intel isn't rushing into it?

We know this for a long time. Few years down the road in sub 10nm, we will reach the era where we cant shrink transistor endlessly. The problem with chip stacking on die is how to get rid of the heat passing through each layer.<p>Stacking in itself has proven to be feasible by the Memory Cube. Where Heat isn't much of a concern.

Wasn't that one of the innovations of Apple's A4 chip? Stacking the RAM chips on top of the CPU core inside the same package?

Hasn't chip stacking been the future of computers for 10 years? Especially of SoC solutions.