VLSI Physical Design

This plus the Verilog to Routing that was posted yesterday showcase the algorithms used in chip design (this post being more about the physical side, v2r covering frontend synthesis as well). The field of Electronic Design Automation (EDA) has some of the most interesting, hardest problems in tech, yet the pay in EDA is kind of mediocre. And EDA is essential in developing new chips -&gt; Semiconductors are essential to our economy.<p>The EDA companies complain about not being able to attract new talent, but maybe if they paid better? The other problem with the EDA companies (as someone who has worked in EDA in the past) is that they&#x27;re just plain stodgy - they feel like some kind of old boys club. We had C++ code from the early 90s and to a large extent they still coded C++ in a 90s style. C++ Templates? Nope, not allowed in the group I was in.

For timing specifically, I recommend &quot;Static Timing Analysis for Nanometer Designs: A Practical Approach&quot; by Bhasker and Chadha.<p><a href="https:&#x2F;&#x2F;link.springer.com&#x2F;book&#x2F;10.1007&#x2F;978-0-387-93820-2" rel="nofollow noreferrer">https:&#x2F;&#x2F;link.springer.com&#x2F;book&#x2F;10.1007&#x2F;978-0-387-93820-2</a><p>It doesn&#x27;t really focus on theory but more the principles of timing analysis and how to wrangle chip design tools into complying with your desired compromises in order to achieve your goals.

This looks like a treasure trove on what it takes in terms of algorithms to enable tools like Cadence Innovus or Synopsys ICC. It’s not a user guide on how to use these tools, but rather a perk behind the curtain.<p>I’ve worked with Andrew, one of the authors on occasion in the past, and he and his team of students are among the best academic teams in the world on this topic.<p>I do think a lot of the secret sauce lives as trade secret with Cadence, Synopsys, Mentor… They see all the real problems in designs from all their customers in bleeding edge nodes like 3nm and beyond.

I hope the developers of KiCad are taking note. It would be amazing to have these placement&#x2F;routing capabilities at the PCB level also.