Zero ASIC is out of stealth

Just to check my understanding -- there&#x27;s a 10x10 mm active interposer here, which has 64 &quot;management-class&quot; (MMU-less, I assume) cores, a crapload of interconnect, and a decent amount of I&#x2F;O; and this can support up to a 5x5 array of chiplets bonded on top, each of which (of the current three) is either a quad core &quot;application-class&quot; processor (but still in-order), a tiny little FPGA (big question seems to be the width&#x2F;capability of the DSP blocks), or something AI-ish that doesn&#x27;t really interest me. Yes?<p>One question that immediately comes to mind is if there are a few pins on the interposer that are basically pass-through to the 2 x 2 mm chiplet on top, so that a chiplet that provides some level of I&#x2F;O beyond what the interposer already has can be supported. I assume the UCIe links or something can be used as generic high speed SERDESes for that sort of use case, but more thinking about radar FEs and such.

Andreas Oloffson was behind the Parallela project as well... <a href="https:&#x2F;&#x2F;parallella.org&#x2F;blog&#x2F;" rel="nofollow noreferrer">https:&#x2F;&#x2F;parallella.org&#x2F;blog&#x2F;</a>

All the machine vision sensor companies use FPGA, which burns huge amount of power. Like 5w when it could be milliwatts.<p>I hope these guys have some ASIC modules for interfacing with CMOS global shutter sensors. Damn if they did I might start a machine vision cam company myself

This is Andreas Olofsson at ZA, ama...

Oh man. I want to love this, but SiFive sort of killed me on treating fabless semiconductor companies as SaaS plays.

I thought custom ASIC&#x27;s were done when you have some computation that takes many instructions to implement in a CPU, for example for Bitcoin mining your computation might be &quot;Find the sha256 of a fixed-length input and tell me if it begins with at least 32 zeros.&quot; The main benefit of using an ASIC (as opposed to an FPGA) is you can hard-wire the circuits, the FPGA has to use generic hardware (super-flexible LUT&#x27;s and a super-flexible routing fabric) and you pay for all that flexibility with speed, power consumption and area.<p>I guess the main benefit of the chiplet idea is that you can get a really fast, low-latency connection between the CPU and FPGA? What kinds of problems can be solved with that architecture, that can&#x27;t be solved by just putting the CPU and FPGA as separate chips on the same circuit board?<p>Or is it cost and design simplicity, you can have a lot of chiplet elements on the same chip, and the customization is in which chiplets you want (&quot;give me a chip with 4xFPGA and 6xCPU&quot;) and how they&#x27;re connected (&quot;CPU A should be connected to FPGA #4, CPU B should be connected to FPGA #2 and #3&quot;)?

Curious to know how well this supports hybrid designs. No-code “IP block” composition is great for some stuff but there’s going to be customisations that aren’t on the standard “blocks”. That said, cool to see this emerge.

To be clear, this is unrelated to the Zero To ASIC course and online community, right?<p>The name collision is a bit annoying.

&gt; <i>Customized ASICs sampling in Q3 2024.</i>

It looks like there&#x27;s something interesting here, but I&#x27;m not really seeing what it is.<p>Can someone explain in simple terms what&#x27;s the added value, compared to buying an FPGA with an embedded RISC-V core? Like, if you want maximum configurability, you already have FPGAs, and if you want maximum performance, you have ICs. Where does Zero ASIC come in? How does it push the Pareto frontier? Is it for prototyping or for final products?

The big question is what do these sell for? Cost dictates how broadly these can be used.

Someone explain why this is a big deal?

Congrats Zero ASIC team!

LinkedIn oauth makes the login a little scary:<p>OAuthZeroASIC would like to: Use your name and photo<p>How are they going to use my name and photo?

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Everything RISC-V is good. But we should go always for 64bits even if we &quot;waste&quot; some &quot;logic material&quot;, because RISC-V as a worldwide&#x2F;licence free standard is a very good ground for an assembly realm: write 64bits RISC-V once and run it on embeded&#x2F;desktop&#x2F;server&#x2F;etc. Just need clean tables of functions for platform mobility which can be added slowly step by step.<p>The main pitfall while doing that, is abusing the preprocessor, because writting &quot;c++&quot; using a preprocessor assembly is hardly less worse than coding c++ then creating a absurdely massive and complex SDK dependency.