A Simulated Annealing FPGA Placer

Simulated annealing has been useful for decades. My undergrad VLSI project was to lay out a 32-bit CRC chip and test it with SPICE (an analog simulation tool). To get the capacitance down, you need short wires. But a CRC-32 has many many interdependencies. Laying one out by hand would take a very very long time.<p>So my partner wrote the Verilog code for the annealer and I wrote a C++ program that attached virtual springs to each gate, iteratively moving gates closer together if they were far apart. At first, the movements are dramatic, but over time, the total length of all gates converges onto an asymptotic limit that is much better than the starting point.<p>Once we had a gate layout implemented in an obscure EDM language, we were able to bring it into SPICE and damn right it worked the first time! I think the professor was somewhat mystified why we didn’t just build a simple 4-bit adder instead, but spend 50 hours on this project was a lot more fun than doing a hand layout.

I used simulated annealing in my previous work doing molecular dynamics- it was great for not getting your protein trapped in a local minima, which gradient descent is prone to doing. I got excellent results for very little work.<p>I asked my intern, who was knowledgeable in deep networks as well as molecular stuff, &quot;it looks like ML training mainly does gradient descent, how can that work, don&#x27;t you get stuck in local minima?&quot; and they said &quot;loss functions in ML are generally believed to be bowl-shaped&quot; and I&#x27;ve been wondering how that could be true.<p>It&#x27;s interesting to read up on the real-world use of annealing for steel - it&#x27;s quite intersting how you can change steel properties through heat treatment. Want it really strong? Quench it fast, that will lock it into an unstable structuer that&#x27;s still strong. Quench it slow, it will find a more stable minimum, and be more ductile.

Does this actually result in a routable design when used on a real FPGA?<p>Optimizing for the lowest value of a distance metric isn&#x27;t necessarily going to be ideal - a highly compact placement (like the results shown) is going to require a lot of wires to pass through the center of the design. Some FPGAs may not have sufficient routing resources to support this, especially if there are many wires that cross over the center without interacting with it.

My understanding of simulated annealing is that solutions that are not improvements are still accepted with some probability in early steps but that this probability decreases as &quot;temperature&quot; drops. Looking at your description (but not code) I did not see that aspect but it looked like you would only accept improvements of the cost function. Is this correct or where does your solution accept slight regressions with some probability, too?

My final year undergrad project (1992?) used an FPGA. The router for that used simulated annealing.

To the author: the source link <a href="https:&#x2F;&#x2F;github.com&#x2F;stefanpie&#x2F;sa-placer">https:&#x2F;&#x2F;github.com&#x2F;stefanpie&#x2F;sa-placer</a> appears to be private.

If you&#x27;re getting into the territory of Global Optimization algorithms like SA it can be helpful to implement your problem generically enough that it can be plugged into a general purpose optimization package like pagmo2, where you can experiment with a dozen or more similar algorithms.

Wondering how this compares to nextpnr (<a href="https:&#x2F;&#x2F;github.com&#x2F;YosysHQ&#x2F;nextpnr">https:&#x2F;&#x2F;github.com&#x2F;YosysHQ&#x2F;nextpnr</a>) ?

force&#x2F;spring based placement also seems to work pretty well- surprised that wasnt simpler to implement as a toy method

Do any methods exist that utilize deep learning to drive the optimization?