Logik: Open-source FPGA toolchain by Zero ASIC

This doesn&#x27;t appear to support any FPGAs other than their FPGA chiplet [1]. Also, like UncleOxidant said, the most complex parts of this toolchain are just existing open-source tools (Yosys and VPR).<p>This seems like a useful toolchain for ZeroASIC customers who are using their hardware, but not for FPGA enthusiasts more broadly.<p>[1]. <a href="https:&#x2F;&#x2F;www.zeroasic.com&#x2F;chiplets&#x2F;fpga" rel="nofollow">https:&#x2F;&#x2F;www.zeroasic.com&#x2F;chiplets&#x2F;fpga</a>

I use to say this whenever I see anything related to FPGA: the FPGA world needs it&#x27;s equivalent to Arduino. Before the Arduino, the world of microcontrollers was dominated by bad proprietary tools; the FPGA world suffers of the same illness today.<p>We really need to fix this before FPGA&#x27;s falls in the hands and hearts of any willing hobbyist.

Haha, cool to see this on HN.:-)<p>Yosys and vpr is clearly doing the heavy lifting here...the novelty here is the fact that an FPGA startup is giving public access to the fpga pre production and is opening the bit stream format. This hasn&#x27;t really been done before.

In computer programming, you can get say a ~10x speed improvement between writing bit twiddling code in python and hand writing SIMD assembly to do the same job.<p>Is there a similar gaping gap between writing verilog for something, vs hand-designing the lookup tables and laying out the FPGA routing?

Isn&#x27;t it Yosys and VPR doing the heavy lifting here?

What are the advantages of this? e.g. How does this compare to using a Makefile?<p>(which is what I&#x27;ve been doing so far, and does not feel complex)