To clear up some possible confusion, seen in discussions elsewhere.<p>This is a bug specific to a microarchitecture, not the RISC-V spec.<p>It affects a specific microarchitecture's implementation of a custom Vector extension, not the RISC-V Vector spec.<p>This custom Vector extension is based in a draft of RISC-V Vector spec with a bunch of THead-specific modifications/additions. It is not based on nor compatible with the ratified RISC-V Vector spec.<p>There's nothing to suggest there's anything inherently wrong with RISC-V spec, or even that any microarchitectures outside of THead's could be affected.<p>Additionally, there are no known implementations of THead custom vector extension outside of THead's own microarchitectures.