科技回声

This is the RISC-V core used in the RP2350, the new Raspberry Pico 2 SoC.

Would be interesting to know what verification they've done on this core. Given it's included as a bonus feature presumably they haven't done full DV on it.<p>The repository has a testbench for running binaries, which includes the RISC-V compliance suite plus some usage of RISCV formal <a href="https://github.com/YosysHQ/riscv-formal">https://github.com/YosysHQ/riscv-formal</a> which is intriguing. Though nothing obvious of the level you'd need to close production level verification on a design.

Amazing that it's apparently implemented in plain Verilog, not SystemVerilog; or did I miss something? Would be interesting to hear from the author what the motivation was for this choice.

Any ideas about why the cores have been included? The best I can come up with is de-risking shipping RISC-V by doing a trial run.<p>What are the rational use-cases for these cores, do they use less power?

Can't wait to see how somebody hacks it to run code on all four cores at the same time. If this is technically/physically possible.

This is the RISC-V core used in the RP2350, the new Raspberry Pico 2 SoC.

Amazing that it's apparently implemented in plain Verilog, not SystemVerilog; or did I miss something? Would be interesting to hear from the author what the motivation was for this choice.

Can't wait to see how somebody hacks it to run code on all four cores at the same time. If this is technically/physically possible.

Hazard3: 3-stage RV32IMACZb* processor with debug

5 条评论

Hazard3: 3-stage RV32IMACZb* processor with debug

5 条评论