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The Memory Wall: Past, Present, and Future of DRAM

106 点作者 klelatti8 个月前

8 条评论

magicalhippo8 个月前
Back when I was young, which isn&#x27;t <i>that</i> far ago, one tried to put as much pre-computed stuff into memory as it was much faster than the CPU. Lookup tables left, right and center.<p>These days you can do thousands of calculations waiting for a few bytes of memory. And not only is the speed difference getting worse, but memory sizes aren&#x27;t keeping up.<p>Guess we&#x27;re not far away from compressing stuff before putting it in memory is something you&#x27;d want to do most of the time. LZ4 decompression[1] is already just a factor of a few away from memcpy speed.<p>[1]: <a href="https:&#x2F;&#x2F;github.com&#x2F;lz4&#x2F;lz4">https:&#x2F;&#x2F;github.com&#x2F;lz4&#x2F;lz4</a>
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ksec8 个月前
I have been stating this for at least 12+ years now. On HN and in many places. And it is still not common knowledge. Hopefully this article get spread and reposted many times in the future.<p>DRAM isn&#x27;t getting (much) cheaper. And it will continue to be the case in next 10 years. Considering there is nothing on the roadmap to suggest any breakthrough.<p>People old enough may remember in the late 00s and even up to mid 10s, there are words like we will get 16GB computer as baseline, or I could work with 64GB soon.<p>Reality is that DRAM price has fluctuate lately within the same range in the past ~13 years. It was only in 2023 the price floor broke through the $2&#x2F;GB barrier.<p>Unless we somehow found a way that could magically shrink the capacitor by a substantial amount. Or we change the way we do programming.
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imtringued8 个月前
I&#x27;m curious if it is possible to design an AI accelerator built around ROM that is programmable via maskless lithography. The idea being that 90% of the chip is being produced using conventional mask based semiconductor technology, but the data is written through electron beam lithography.<p>Given a regular ROM structure on the silicon wafer, it would be possible to take advantage of parallel beams and design an electron beam lithography machine specifically for ROM to reduce the cost of programming. The final frontier would be to build a &quot;wafer scale engine&quot;-esque single wafer chip and we would have essentially reached the limits of what is achievable through clever design of silicon based semiconductors.
sevensor8 个月前
Compute in memory is exciting, but it’s going to be hard to pull off. Transistors go underneath capacitors, which means they have to survive the subsequent fabrication of the capacitors without thermal processing disrupting their carefully engineered dopant profiles. It’s not just conservatism that keeps on die logic simple. Bonding, as suggested by the article, is probably the only option, but that brings some absolutely hilarious alignment issues along with it. I’m sure it’s coming, but it won’t be cheap.
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rayiner8 个月前
Can someone explain like I’m five why DRAM latency basically hasn’t improved in decades? I remember 60ns FPM SIMMs in our 486 back in the 1990s. Doesn’t seem any faster now.
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hulitu8 个月前
What happened to SRAM ?
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deater8 个月前
if Sally Mckee, who coined the term &quot;Memory Wall&quot;, had a nickel for each time it gets mentioned, she&#x27;d have a lot of nickels
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didgetmaster8 个月前
I think that &#x27;memory wall&#x27; is completely different from &#x27;memory hole&#x27;, but I forget how.
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