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Automated feature testing of Verilog parsers using fuzzing

15 点作者 matt_d9 个月前

2 条评论

eigenform9 个月前
Reminds me that we&#x27;re definitely overdue for replacing Verilog with something more deserving of the title &quot;universal IR for EDA&#x2F;hardware design tools&quot;<p>Can&#x27;t help but feel like there&#x27;s some kind of Conway&#x27;s Law type-of-thing here: industry didn&#x27;t evolve to be as &quot;open&quot; as software, so the interfaces are largely a function of the historical momentum of things.
AgentOrange12349 个月前
Welp, this is going to be a miserable slog.<p>I had the misfortune of writing a SystemVerilog parser once upon a time. The grammar is a huge and ambiguous muddle. SVA is a beast with no clear precedence on some of the operators. The standard&#x27;s description of the preprocessor is an incoherent mess.<p>Godspeed!