Curiously, instead of "set capture reg, wait for clock edge, read", the "read reg twice, until same result is obtained" approach is ignored. This is strange as it is usually much faster - reading a 3.25MHz counter at 200MHz+ twice is very likely to see the same value twice. For a 32KHz counter, it is basically guaranteed.<p><pre><code> u32 val;
do {
val = readl(...);
} while (val != readl(...));
return val;
</code></pre>
compiles to a nice 6-instr little function on arm/thumb too, with no delays<p><pre><code> readclock:
LDR R2, =...
1:
LDR R0, [R2]
LDR R1, [R2]
CMP R0, R1
BNE 1b
BX LR</code></pre>