A FPGA friendly 32 bit RISC-V CPU implementation

6 years ago, I wrote an in-depth blog post about the design principles of the Vexriscv. It’s unlike any other CPU I’ve seen.<p><a href="https:&#x2F;&#x2F;tomverbeure.github.io&#x2F;rtl&#x2F;2018&#x2F;12&#x2F;06&#x2F;The-VexRiscV-CPU-A-New-Way-To-Design.html" rel="nofollow">https:&#x2F;&#x2F;tomverbeure.github.io&#x2F;rtl&#x2F;2018&#x2F;12&#x2F;06&#x2F;The-VexRiscV-CP...</a>

The most interesting thing about this isn’t that it’s a RISC-V implementation but that it’s written in a Scala HDL language, SpinalHDL. There are quite a few of these now - Chisel (which Spinal forked from long ago), Amaranth (Python), and Clash (Haskell) all come to mind.

There is a successor project as well: <a href="https:&#x2F;&#x2F;github.com&#x2F;SpinalHDL&#x2F;VexiiRiscv">https:&#x2F;&#x2F;github.com&#x2F;SpinalHDL&#x2F;VexiiRiscv</a>

Latest presentation on this topic by main developer:<p><a href="https:&#x2F;&#x2F;youtu.be&#x2F;dR_jqS13D2c?si=bbZf7Oo5a3JsINYs" rel="nofollow">https:&#x2F;&#x2F;youtu.be&#x2F;dR_jqS13D2c?si=bbZf7Oo5a3JsINYs</a>

Fits on an ICE-40 fpga, that’s not nothing!

What does &quot;FPGA friendly&quot; mean? I tried to figure it out from the README, which says &quot;Implement multiplication using multiple sub multiplication operations in parallel (&quot;FPGA friendly&quot;)&quot;. Put another way: what is the FPGA-UNfriendly way to do multiplication?

How does it compare to the many other RISC-V CPUs?

I find it fascinating, calling a CPU implementation FPGA friendly. I don&#x27;t know why everybody always wants to run soft CPU&#x27;s on an FPGA.<p>I mean I understand that its nice for the development stage of a CPU, but for all practical purposes, a FPGA is a thing where you can do hyper specialized things in massively parallel fashion, and essentially don&#x27;t do something to run general purpose code.<p>I am not saying that people should stop doing this things, everybody is free to do what they want, still i don&#x27;t understand why most of FPGA talks are about soft CPU&#x27;s when the really interesting stuff is something completely different.

Saw .scala files and thought &quot;some verilog thing that uses that extension&quot;. Nope. Lots of Scala. That&#x27;s not what I expected!

It reminded me of how, a long time ago, FPGAs were used in Bitcoin mining.