T1: A RISC-V Vector processor implementation

It&#x27;s a legacy processor, but the UltraSPARC T1 is the first thing I thought of when I saw the title...<p><a href="https:&#x2F;&#x2F;en.m.wikipedia.org&#x2F;wiki&#x2F;UltraSPARC_T1" rel="nofollow">https:&#x2F;&#x2F;en.m.wikipedia.org&#x2F;wiki&#x2F;UltraSPARC_T1</a><p>This legacy CPU is actually open source, along with its successor, the T2.<p><a href="https:&#x2F;&#x2F;www.oracle.com&#x2F;servers&#x2F;technologies&#x2F;opensparc.html" rel="nofollow">https:&#x2F;&#x2F;www.oracle.com&#x2F;servers&#x2F;technologies&#x2F;opensparc.html</a>

Here is a list of open sourve RVV implementations: <a href="https:&#x2F;&#x2F;github.com&#x2F;stars&#x2F;camel-cdr&#x2F;lists&#x2F;rvv-implementations">https:&#x2F;&#x2F;github.com&#x2F;stars&#x2F;camel-cdr&#x2F;lists&#x2F;rvv-implementations</a><p>They have varying progress and target performance.

Might be interesting to see this combined with vex. Also nice to see the recognition that memory bandwidth is an important consideration.

Am I understanding the README correctly in that:<p>You can execute some nix commands to fire up an emulator for this CPU design? That&#x27;s pretty cool, I wonder how hard it&#x27;d be to reduce it to a docker command?<p>Also, I&#x27;d never heard of Chisel but it looks amazing - software defines hardware via a Python-esque DSL to Verilog compiler.<p><a href="https:&#x2F;&#x2F;github.com&#x2F;chipsalliance&#x2F;chisel">https:&#x2F;&#x2F;github.com&#x2F;chipsalliance&#x2F;chisel</a>

Would love to have seen some benchmarks.

Previously (name-wise): <a href="https:&#x2F;&#x2F;en.wikipedia.org&#x2F;wiki&#x2F;UltraSPARC_T1" rel="nofollow">https:&#x2F;&#x2F;en.wikipedia.org&#x2F;wiki&#x2F;UltraSPARC_T1</a><p>tl;dr - a 32-thread SPARC cpu from 20 years ago, with subsequent chips getting to 256 threads per chip

Very cool