Run RISC-V Binaries on AMD Zen-Series CPUs via Microcode Modification

This is not achievable.<p>There isn&#x27;t enough rewritable microcode to do this even as a super slow hack.<p>And even if all of the microcode were rewritable, ucode is kind of a fallback pathway on modern x86 cores with the fast path being hardwired decode for x86 instructions.<p>And even if that weren&#x27;t the case the microcode decode and jump is itself hardwired for x86 instruction formats.<p>And even if that weren&#x27;t the case the microops are very non-RISC being 2 address, etc.

Transmeta out here snickering that it took people this long to think of this.

The ISA front-end is not strongly coupled and the original zen had a canceled version that used aarch64.

This type of contest style recruiting just seems like a way to trick people into writing code for free, and even if you do win the prize money seems laughably small for what they&#x27;re asking to receive.

I think a more realistic thing would be adding a few custom OPs to make binary rewriting more performant.<p>Another interesting thing would be implementing a subset of RVV with AVX512 hardware primitives, although idk if&#x2F;how they are exposed in micro code, amd you likely would need to use a different instruction encoding.

Unrealistic, yet amusing.<p>Fortunately, they aren&#x27;t betting everything on this approach.