Subnanosecond Flash Memory

<i>to demonstrate that the device remains stable even after 60,000s</i><p>A little over 16 hours? That&#x27;s suspiciously short. The endurance vs retention curve isn&#x27;t clear from this article either; they say &quot;10 years&quot; and &quot;5.5 million cycles&quot; but it seems more like you either get 10 years and 1 cycle, or 5.5M cycles to immediate failure with no regard to retention.<p>It reminds me of this old paper on testing USB drives for endurance, where they just hammered at the flash until it failed to program immediately and &quot;concluded&quot; that the endurance was many orders of magnitude higher than the manufacturer&#x27;s specifications, with no attention paid to retention at all: <a href="https:&#x2F;&#x2F;www.usenix.org&#x2F;event&#x2F;fast10&#x2F;tech&#x2F;full_papers&#x2F;boboila.pdf" rel="nofollow">https:&#x2F;&#x2F;www.usenix.org&#x2F;event&#x2F;fast10&#x2F;tech&#x2F;full_papers&#x2F;boboila...</a>

Recent discussion:<p>Researchers develop picosecond-level flash memory device (19.04.2025)<p><a href="https:&#x2F;&#x2F;news.ycombinator.com&#x2F;item?id=43735452">https:&#x2F;&#x2F;news.ycombinator.com&#x2F;item?id=43735452</a>

Assume the memory is instant. We still need to communicate with it across physical distance. How far away the memories are in space is way more critical than the speed of any one element in isolation.<p>Why are we constrained to such a relatively small amount of L1 cache? What would stop us from extending this arbitrarily?

&gt; The Dirac channel flash shows a program speed of 400 picoseconds, non-volatile storage and robust endurance over 5.5 × 10^6 cycles.

And then throw in some co-located compute there using chiplets, entirely bypassing the memory bus and PCIe. That&#x27;d be _the_ ideal Transformer substrate. Memory bandwidth bottleneck just disappears for the most part. Memory size bottleneck, too.