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Why Intel is adding instructions to speed up non-volatile memory

118 点作者 joe_bleau超过 10 年前

7 条评论

bahahah超过 10 年前
There are several storage class memories that are nearing commercialization. Intel is betting big on at least one of them. Most technologies in this class are orders of magnitude faster and have orders of magnitude better endurance than flash memory, while being only slightly slower the DRAM, yet non-volatile.<p>It is plausible that with another layer of in-package cache they could eliminate DRAM altogether, replacing it with ultrafast NVM. Imagine the resume&#x2F;suspend speed and power savings of a machine whose state is always stored in NVM.
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sweis超过 10 年前
I&#x27;ve heard predictions that a significant portion of new x86 servers will be using non-volatile memory within the new 5-7 years.<p>Memory is becoming the new disk. This could have major security implications, as memory contents are unencrypted in general.<p>Fortunately, Intel CPUs will have hardware support to encrypt SGX enclaves. Perhaps that support can be used for general memory access as well.
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Animats超过 10 年前
Computing really hasn&#x27;t figured out how to handle non-volatile memory as yet. It&#x27;s almost always used to emulate rotating disks, with file systems, named files, and a trip through the OS to access anything. Access times for non-volatile memory are orders of magnitude faster than disk access times, so small accesses are feasible. But that&#x27;s not how it&#x27;s treated under existing operating systems.<p>There are alternatives. Non-volatile memory could be treated as a key&#x2F;value store, or a tree, with a storage controller between the CPU and the memory device. With appropriate protection hardware, this could be accessed from user space through special instructions. That&#x27;s what I though this article indicated. But no. This is just better cache management for the OS.
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unwind超过 10 年前
Very interesting! It&#x27;s always fun to see &quot;external&quot; development in the general field of computer architecture affect low-level stuff like a CPU&#x27;s cache and memory subsystems.<p>It wasn&#x27;t super-easy to figure out <i>who</i> in the grand ecosystem view of things is going to have to care about these instructions, but I guess database and OS folks.<p>Also, if the author reads this, the first block quote with instruction descriptions has an editing fail, it repeats the same paragraph three times (text begins &quot;CLWB instruction is ordered only by store-fencing operations&quot;).
0x0超过 10 年前
Isn&#x27;t there a higher risk of data loss, if your &quot;hard drive&quot; is 100% memory mapped - all it would take is one buggy kernel driver writing to an invalid pointer or memset&#x27;ing the whole thing to 0?
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jhallenworld超过 10 年前
Support for non-voltile memory needs to be added to Linux. For example, one should be able to map the non-volatile memory into user space and directly access it. There needs to be some BIOS-OS interaction so that the OS doesn&#x27;t treat the non-volatile memory as general memory (for the likely case where only some of the memory is non-volatile). Alternatively, the non-volatile memory should be usable as a block device.<p>The non-volatile memory needs a layer of RAID-like volume management. For example, when you transfer the memory from one system to another, there should be a way to determine that the memory is inserted in the correct slots (remember there is RAID like interleaving&#x2F;striping across memory modules).
shaurz超过 10 年前
How to solve the context switch overhead issue: <a href="https://www.destroyallsoftware.com/talks/the-birth-and-death-of-javascript" rel="nofollow">https:&#x2F;&#x2F;www.destroyallsoftware.com&#x2F;talks&#x2F;the-birth-and-death...</a>
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