My thoughts on the matter:<p>Given that process sizes keep shrinking, and every time you shrink the process size you can fit more on the chip, and heat doesn't scale (as in, the smaller the process size the more heat per in^2), and we're up against a heat wall as it is, we're to the point now where a large chunk of the chip <i>has</i> to be dark at any point in time. As such, CISCs are looking better and better. Because you cannot really scale frequency more (due to heat concerns - freq^2 heat output, to a first approximation), and you have to run most of the chip dark at a time <i>anyways</i>, and you have the space, so you may as well have things that are optimized for rare use cases. And we're already seeing that. The micro-ops on modern x86 processors are getting more and more complex and specialized.<p>This will especially start happening once we get decent CPU caches - the 3d-ish stacks that are being talked about. Where you have a separate chip stacked under or over the CPU that has a process optimized for RAM.<p>Note that this is <i>not</i> talking about ISAs, this is talking about the processor itself. Although it's not done much currently, you can just as easily (or rather, with just as much effort) convert a RISC into CISC-like micro-ops (macro-ops?) as convert a CISC into RISC-like micro-ops. It's looking more and more as though ISAs can be successfully decoupled from the actual processor design. Which is encouraging. Treat the instruction encoding as effectively a compression scheme for the instructions that the actual processor runs.